Low-Power and Space-Efficient Built In Self-Test Architecture With MSIC Test Pattern Generator

Main Article Content

Kolanchinathan V P
Associate Professor, Department Of Electronics And Communication Engineering, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai, India

Dinesh Kumar T R
Associate Professor, Department Of Electronics And Communication Engineering, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai, India

Jaishree P
UG Students, Department Of Electronics And Communication Engineering, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai, India

Niranjana M
UG Students, Department Of Electronics And Communication Engineering, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai, India

Sowmiya M
UG Students, Department Of Electronics And Communication Engineering, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai, India

Thresha V
UG Students, Department Of Electronics And Communication Engineering, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai, India

Pooja sri K
UG Students, Department Of Electronics And Communication Engineering, Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai, India

Keywords

BuiltInSelfTest(BIST), Multiple single input change(MSIC), Test pattern generator(TPG), fault coverage, pseudorandom test pattern

Abstract

The new low-cost test pattern generation approach for a Multiple Single Input Change (MSIC) test pattern BIST architecture. BIST is a methodology that uses on-chip test logic to identify problematic system components. To increase fault coverage, the authors propose using a test pattern generator that creates MSIC test patterns and weights the pseudorandom test patterns. The goal is to provide an effective weighted TPG for a BIST architecture based on scans that requires less space and power usage. To maximize the length of the weighted pseudorandom patterns, the authors use a TPG pseudo-primary seed and a weight-enabled clock to provide distinct weights to the various scan chains. By this method, the hardware overhead is decreased and 0.215 μW power usage is achieved . The proposed weighted TPG produces accurate results when applied to two alternative test-per-scan BIST architectures, with fewer switching transitions, larger fault coverages, and less delay of 0.170 μs and area compared to existing methods. This behavior is observed for six additional circuits being tested. In order to compare the suggested balanced TPG with other potential designs, it is also scaled up to a larger bit TPG. The experimental findings are compared and contrasted with those of other TPG designs.

Abstract 96 | pdf Downloads 172

References

1. G. Harutyunyan, S. Shoukourian and Y. Zorian, "Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 3, pp. 562-575, March 2019, doi: 10.1109/TCAD.2018.2818688.
2. M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand and H. -J. Wunderlich, "Built-In Test for Hidden Delay Faults," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 10, pp. 1956-1968, Oct. 2019, doi: 10.1109/TCAD.2018.2864255.
3. H. Kondo et al., "A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted Processor Supporting ISO26262 ASIL D," in IEEE Journal of Solid-State Circuits, vol. 55, no. 1, pp. 133-144, Jan. 2020, doi: 10.1109/JSSC.2019.2953826.
4. V. Shivakumar, C. Senthilpari and Z. Yusoff, "A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture," in IEEE Access, vol. 9, pp. 29366-29379, 2021, doi: 10.1109/ACCESS.2021.3059171.
5. G. N. Balaji and S. C. Pandian, ‘‘Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates,’’ Cluster Comput., vol. 22, no. S6, pp. 15231–15244, Nov. 2019, doi: 10.1007/s10586-018-2552-x.
6. X. Lin and J. Rajski, ‘‘Adaptive low shift power test pattern generator for logic BIST,’’ in Proc. Asian Test Symp., 2010, pp. 355–360, doi: 10.1109/ATS.2010.67.
7. S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, and T. I. M. Imag, ‘‘Multiple-polynomial linear feedback shift registers,’’ 1992, pp. 120–129
8. G. S. Sankari and M. Maheswari, ‘‘Energy efficientweighted test pattern generator based bist architecture,’’ in Proc. Int. Conf. I-SMAC (IoT Soc. Mobile, Anal. Cloud), I-SMAC, 2019, pp. 448–453, doi: 10.1109/ I-SMAC.2018.8653768.
9. A. S. Abu-Issa, ‘‘Energy-efficient scheme for multiple scan-chains BIST using weight-based segmentation,’’ IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 65, no. 3, pp. 361–365, Mar. 2018, doi: 10.1109/TCSII.2016. 2617160.
10. A. Jas, C. V. Krishna, and N. A. Touba, ‘‘Weighted pseudorandom hybrid BIST,’’ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 12, pp. 1277–1283, Dec. 2004, doi: 10.1109/TVLSI.2004.837985.
11. R. Kapur, S. Patil, T. J. Snethen, and T. W. Williams, ‘‘A weighted random pattern test generation system,’’ IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 15, no. 8, pp. 1020–1025, Aug. 1996, doi: 10.1109/43.511581.
12. H.-C. Tsai, K.-T. Cheng, and S. Bhawmik, ‘‘On improving test quality of scan-based BIST,’’ IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 8, pp. 928–938, Aug. 2000, doi: 10.1109/ 43.856978
13. D. Xiang, M. Chen, and H. Fujiwara, ‘‘Using weighted scan enable signals to improve test effectiveness of scan-based BIST,’’ IEEE Trans. Comput., vol. 56, no. 12, pp. 1619–1628, Dec. 2007.
14. G. Kiefer, H. Vranken, E. J. Marinissen, and H. J. Wunderlich, ‘‘Application of deterministic logic BIST on industrial circuits,’’ J. Electron. Test. Theory Appl., vol. 17, nos. 3–4, pp. 351–362, 2001, doi: 10.1023/A:1012283800306.
15. N. A. Touba and E. J. McCluskey, ‘‘Altering a pseudo-random bit sequence for scan-based BIST,’’ in Proc. IEEE Int. Test Conf., Oct. 1996, pp. 167–175, doi: 10.1109/test.1996.556959.
16. B. W. Johnson, J. H. Aylor, and H. H. Hana, ‘‘Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder,’’ Comput. Arith., vol. 23, no. 1, pp. 171–178, 2015, doi: 10.1142/9789814641470

Article Sidebar

pdf
Published
May 5, 2023
DOI https://doi.org/10.47750/jptcp.2023.30.09.031

Article Details

How to Cite
Kolanchinathan V P, Dinesh Kumar T R, Jaishree P, Niranjana M, Sowmiya M, Thresha V, & Pooja sri K. (2023). Low-Power and Space-Efficient Built In Self-Test Architecture With MSIC Test Pattern Generator. Journal of Population Therapeutics and Clinical Pharmacology, 30(9), 308–314. https://doi.org/10.47750/jptcp.2023.30.09.031
Issue
Vol. 30 No. 9 (2023): JPTCP
Section
Articles
Creative Commons License

This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.

All articles published in JPTCP  are licensed under Copyright Creative Commons Attribution-NonCommercial 4.0 International License.

Most read articles by the same author(s)